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FUJITSU SEMICONDUCTOR DATA SHEET
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DS04-22115-4E
MB86978A
DESCRIPTION
MB86978A is IPsec accelerator engine of Inline Architecture. Once setup with appropriate parameters, the device can perform bi-directional 100 Mbps IPsec processing at full wire speed.
FEATURES
* Built-in RMII/MII interface of two ports
One interface for WAN (internet) side and one for routing function side * Complies with IEEE802.3 (DIX format) * Supports 10/100BASE-T/TX, full/half-duplex, and auto-negotiation * IEEE 802.3x flow control supported * Half-duplex back pressure supported * SMI interface for PHY device control
PACKAGE
337-pin plastic FBGA
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(Continued)
288-pin plastic FBGA
BGA-337P-M02
BGA-288P-M13
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MB86978A
* Built-in engine for IKE processing To speed up the calculation processing of IKE, the following functional block is built-in. When IPsec is processed in host CPU, this encryption engine and the authentication engine can be used. * DES/3DES : Encryption engine * AES : Encryption engine * SHA-1 : Authentication engine * MD5 : Authentication engine * IKE support : Surplus operation engine for RSA and DH processing acceleration * Built-in Inline type IPsec processing engine To execute the IPsec processing of a full wire with Inline IPsec, the following functions are installed. (1) Full wire code engine DES/3DES (CBC mode) AES (CBC mode, Length of key128/192/256 bit) (2) Full wire attestation engine HMAC-SHA-1-96 HMAC-MD5-96 * It provides with the SA (Security association) data base. * SA of 64 can be set. (direction of encode : 64 and decode direction : 64) * IPv4/IPv6 both correspondence * It is possible to correspond to the following modes. - Transport mode (ESP AH, AH, ESP) , - Tunnel mode (ESP AH) , - Transport over tunnel mode * The following parameters can be specified for a selector. Address Internet Protocol address, Transmission former Internet Protocol address, Address TCP/UDP port number, Transmission former TCP/UDP port number, Protocol in AH SPI, ESP SPI, and transport layer, IPsec protocol, TOS field, Flow label, Traffic class * Replay defense function supported * NAT-Traversal supported * IP over PPPoE frame supported * IP over VLAN frame supported * IV value count up mode/random mode supported * The SA database can be expanded To connect the LSI (MB86979) for enhancing SADB externally, the SA database can be enhanced. Up to 4096 (512 x 8) SA can be supported (encode direction : 4096, decode direction : 4096) . * F mode supported The routing function side can add the IPsec SA value to the Ethernet frame as an SA tag and pass this to the MB86978A for IPsec processing. * Packet division supported The packet that does MTU exaggerated size by the IPsec processing is divided in LSI automatically. Processing is performed at wire speed. (Continued)
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MB86978A
(Continued) * Host interface Includes a general-purpose I/O interface for connection to a wide range of CPUs. Capable of switching between 16-bit bus mode and 32-bit bus mode. * Speed-up of routing function part By connecting an external high-speed IP forwarding engine (MB86977) , IPsec processing and routing processing can both be performed bi-directionally at full wire speed. * Others * Process * Power-supply voltage * Operation frequency * Package : 0.18 m process : 1.8 V/3.3 V dual power supplies : Max 66 MHz : 337-pin plastic FBGA, 288-pin plastic FBGA
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MB86978A
PIN ASSIGNMENT
* 337-pin FBGA No. A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 V1 W1 Y1 AA1 AB1 AC1 AD1 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 Symbol N.C. N.C. N.C. GND D0 D2 D4 D7 D10 D13 D16 D19 D22 D25 D28 D30 VDDI VDDI CLK XCS XRE ADD2 ADD5 ADD8 N.C. VDDE ADD10 VDDE XINT SAADD0 SAADD3 SAADD5 SAADD8 No. AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 P25 N25 M25 L25 K25 J25 H25 F25 E25 D25 C25 B25 A25 Pin name CMDD GND CLD2E N.C. VDDI CLD0D CLD2D VDDI N.C. GND VDDE N.C. SAD0 SAD2 SAD4 SAD7 SAD10 SAD13 SAD16 SAD19 SAD22 SAD25 SAD28 SAD30 VDDE VDDE UPRIE XTCK REFCLK N.C. N.C. N.C. N.C. No. A19 A18 A17 A16 A15 A14 A13 A12 A10 A9 A8 A7 A6 A5 A4 A3 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 Pin name VDDI TXENA TXD0A TXD2A TXENB TXD2B VDDE VDDE No. AC2 AD2 AD3 AD4 AD5 AD6 AD7 AD8 Pin name ADD6 ADD9 GND VDDI VDDI SAADD1 SAADD4 SAADD6 SAADD9 No. H24 F24 E24 D24 C24 B24 B23 B22 Pin name UPRID TDI N.C. N.C. N.C. TMS RXCLKA RXD0A RXD2A COLA VDDE VDDE TXD1A TXD3A TXD0B TXD3B VDDI TXCLKB CRSB RXDVB RXD2B MDCB VDDI MDIOA VDDE VDDE N.C. N.C. N.C. N.C. GND D6 D9 No. P3 R3 T3 U3 V3 W3 Y3 AA3 AB3 AC3 AC4 AC5 AC6 AC7 AC8 AC9 Pin name D27 N.C. GND GND VDDI VDDI N.C. VDDE ADD4 ADD7 N.C. N.C. SAADD2 GND SAADD7 SAADD10
G24 XMATCHD
A11 RXCLKB AD9
RXD0B AD10 SAADD12 B21 RXD1B AD11 SAADD15 B20 RXD3B AD12 SAADD18 B19 GND VDDI N.C. VDDI VDDI N.C. N.C. N.C. N.C. D1 D3 D5 D8 D11 D14 D17 D20 D23 D26 D29 D31 GND AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 P24 XSARE XPKTE XPKTD VDDE VDDE CLD3E VDDE VDDE CLD1D CLD3D N.C. N.C. GND SAD1 SAD3 SAD5 SAD8 SAD11 SAD14 SAD17 SAD20 SAD23 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 C3 D3 E3 F3 G3 H3
AC10 SAADD13 AC11 SAADD16 AC12 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AB23 AA23 Y23 W23 N.C. CMDE GND CLD0E CLD1E N.C. N.C. VDDI N.C. N.C. VDDI GND N.C. SAD6 SAD9 (Continued) AC13 XRSTOUT
G25 XMATCHE
AE10 SAADD11
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MB86978A
(Continued) No. Symbol No. A24 A23 A22 Pin name TRST RXDVA RXD1A CRSA TXCLKA TDO TXD1B MDCA VDDI N.C. COLB RXERB VDDE N.C. VDDE MDIOB N.C. N.C. N.C. VDDI GND N.C. No. V2 W2 Y2 AA2 AB2 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 W4 Y4 AA4 AB4 AB5 AB6 Pin name XRST XWE GND ADD3 N.C. GND GND VDDE VDDI GND GND GND N.C. VDDE VDDE N.C. N.C. N.C. N.C. GND VDDI No. N24 L24 K24 J24 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AA22 Pin name SAD26 SAD29 SAD31 VDDI XSAINTE N.C. VDDE GND VDDI N.C. GND GND N.C. N.C. N.C. VDDI VDDI N.C. GND GND VDDE GND No. Y22 J3 K3 L3 M3 N3 W22 V22 U22 T22 R22 P22 N22 M22 L22 K22 J22 H22 G22 F22 E22 D22 Pin name VDDI D12 D15 D18 D21 D24 GND VDDE GND GND N.C. VDDI VDDE GND N.C. GND GND N.C. VDDI N.C. GND VDDI No. D21 V23 U23 T23 R23 P23 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Pin name N.C. SAD12 SAD15 SAD18 SAD21 SAD24 GND GND N.C. N.C. GND N.C. VDDI GND GND N.C. N.C. VPD N.C. N.C. GND GND
AE11 SAADD14 AE12 SAADD17 AE13 XSAWE
MODE16 M24
AE14 XCMDDVE A21 AE15 XCMDDVD A20 N23 M23 L23 K23 J23 H23 G23 F23 E23 D23 C23 C22 C21 C20 C19 C18 C17 SAD27 N.C. VDDI GND XSAINTD N.C. VDDI N.C. N.C. N.C. TCK RXERA RXD3A N.C. VDDI N.C. VDDI C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 D4 E4 F4 G4
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MB86978A
* 288-pin FBGA No. Symbol
A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 V1 W1 Y1 AA1 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 N.C. D0 D1 D2 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 XRST CLK XCS ADD2 ADD5 ADD8 VDDE N.C. VDDI VDDI XINT SAADD0 SAADD3 SAADD6 SAADD9 SAADD12 SAADD15 SAADD18 XCMDDVE
No.
AB18 AB19 AB20 AB21 AB22 AA22 Y22 W22 V22 U22 T22 R22 P22 N22 M22 L22 K22 J22 H22 G22 F22 E22 D22 C22 B22 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
Pin name
CLD2D N.C. VDDE VDDI N.C. SAD0 SAD1 SAD3 SAD6 SAD9 SAD12 SAD15 SAD17 SAD19 SAD22 SAD25 SAD28 SAD30 XSAINTE UPRIE XMATCHE REFCLK N.C. N.C. N.C. N.C. RXERA TCK RXDVA RXD0A RXD2A TXCLKA TXENA TXD2A TXENB TXD2B MDCA TXCLKB
No. Pin name No.
A9 A8 A7 A6 A5 A4 A3 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 RXDVB RXD2B RXERB MDIOA VDDE N.C. N.C. N.C. GND GND D3 D5 D8 D11 D14 D17 D20 D23 D26 D29 VDDE GND GND XWE ADD3 ADD6 ADD9 VDDE VDDE GND SAADD1 SAADD4 SAADD7 SAADD10 SAADD13 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 Y21 W21 V21 U21 T21 R21 P21 N21 M21 L21 K21 J21 H21 G21 F21 E21 D21 C21 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11
Pin name
XPKTD VDDI CLD1E CLD3E CLD1D CLD3D N.C. GND VDDE SAD2 SAD4 SAD7 SAD10 SAD13 SAD16 SAD18 SAD20 SAD23 SAD26 SAD29 SAD31 GND UPRID XSAINTD XTCK N.C. N.C. VDDI TMS RXCLKA RXD1A RXD3A VDDI TXD0A TXD3A TXD0B TXD3B GND
No.
B10 B9 B8 B7 B6 B5 B4 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
Pin name
RXCLKB RXD0B RXD3B MDCB MDIOB VDDE VDDI N.C. N.C. VDDI D6 D9 D12 D15 D18 D21 D24 D27 D30 VDDE GND MODE16 XRE ADD4 ADD7 ADD10 GND SAADD2 SAADD5 SAADD8 SAADD11 SAADD14 SAADD17 XSARE CMDE CMDD VDDI VDDE
No.
Y16 Y17 Y18 Y19 Y20 W20 V20 U20 T20 R20 P20 N20 M20 L20 K20 J20 H20 G20 F20 E20 D20 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4
Pin name
GND VDDE VDDI N.C. GND SAD5 SAD8 SAD11 SAD14 VDDI VDDE SAD21 SAD24 SAD27 GND VDDE VDDI VDDI XMATCHD TDI N.C. TRST VDDI CRSA COLA VDDI TXD1A TDO TXD1B VDDI VDDI CRSB RXD1B COLB GND GND GND VDDI
AB13 XCMDDVD AB14 AB15 AB16 AB17 VDDE CLD0E CLD2E CLD0D
AA10 SAADD16 AA11 AA12 XSAWE XPKTE
(Continued) 6
MB86978A
(Continued) No. Symbol
D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 N.C. GND N.C. GND GND VDDE VDDI GND GND GND
No.
P4 R4 T4 U4 V4 W4 W5 W6 W7 W8
Pin name
VDDI VDDI VDDI VDDI GND N.C. GND VDDI VDDE GND
No. Pin name No.
W9 W10 W11 VDDI GND GND W19 V19 U19 T19 R19 P19 N19 M19 L19 K19
Pin name
N.C. GND N.C. GND GND GND GND VDDI VDDE GND
No.
J19 H19 G19 F19 E19 D19 D18 D17 D16 D15
Pin name
GND VDDI VDDE VDDI GND N.C. VDDE GND VDDE GND
No.
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
Pin name
GND VDDI VDDE VDDE GND VPD VDDE VDDE VDDI VDDI
W12 XRSTOUT W13 W14 W15 W16 W17 W18 GND GND VDDE VDDI VDDI GND
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MB86978A
PIN DESCRIPTION
* Host (SRAM) interface Symbol ADD2 to ADD10 D0 to D31 XCS XWE XRE XINT MODE16 Pin name I/O I I/O I I I O I Description Address input from host CPU Data bus of host CPU Selection signal input from host CPU (Low active) Write signal input from host CPU (Low active) Read signal input from host CPU (Low active) Interrupt output signal to host CPU (Low active) Host CPU bus width selection mode 1 : 16 bit mode, 0 : 32 bit mode
Address Bus Data input/output Chip Select Write Enable Read Enable Host Interrupt Host CPU Bus Mode
* Interface for extended SADB chip connection Symbol Pin name XRSTOUT XCMDDVE CMDE XPKTE XMATCHE CLD0E CLD1E CLD2E CLD3E XCMDDVD CMDD XPKTD XMATCHD CLD0D CLD1D CLD2D CLD3D UPRIE UPRID Reset for Ext-SADB Encryption Command Valid Signal Encryption Command Signal Encryption Packet Valid Signal Ext-SADB Encryption Side Match Signal
I/O O O O O I
Description Reset output signal to extended SADB chip (Low active) Encode side command effective notification signal to extended SADB chip (Low active) Encode side command signal to extended SADB chip Encode side packet effective notification signal to extended SADB chip (Low active) Encode side match signal from extended SADB chip (Low active)
Encryption Classifier Data
Data bus for encode side extended SADB I/O Used when encoding to output the search data and to input the search result from the extended SADB chip. O O O I Decode side command effective notification signal to extended SADB chip (Low active) Decode side command signal to extended SADB chip Decode side packet effective notification signal to extended SADB chip (Low active) Decode side match signal from enhancing SADB chip (Low active)
Decryption Command Valid Signal Decryption Command Signal Decryption Packet Valid Signal Ext-SADB Decryption Side Match Signal
Decryption Classifier Data
Data bus for decode side extended SADB I/O Used when decoding to output the search data and to input the search result from the extended SADB chip. I I The first match signal from encode side of extended SADB chip (High active) The first match signal from decode side of extended SADB chip (High active) (Continued)
Ext-SADB Encryption Side First Match Signal Ext-SADB Decryption Side First Match Signal
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MB86978A
(Continued) Symbol XSAWE XSARE SAADD0 to SAADD18 SAD0 to SAD31 XSAINTE XSAINTD
Pin name Ext-SADB Write Enable Signal Ext-SADB Read Enable Signal Ext-SADB Address Bus Ext-SADB Data Bus Ext-SADB Encryption Side Interrupt Ext-SADB Decryption Side Interrupt
I/O O O O
Description Data write enable signal to extended SADB chip (Low active) Data read enable signal to extended SADB chip (Low active) Address bus to extended SADB chip
I/O Data bus to extended SADB chip I I Interruption signal from encode side of extended SADB chip (Low active) Interruption signal from decode side of extended SADB chip (Low active)
* RMII interface (2 port) Symbol Pin name I/O Description Reference clock input Synchronous signal of RMII when transmitting and receiving Frequency : 50 MHz Transmission data output bus of router side Transmission data output bus of WAN side Transmission enable output of router side (High active) Transmission enable output of WAN side (High active) Reception error input of router side (High active) Reception error input of WAN side (High active) Receive data input bus of router side Receive data input bus of WAN side Carrier sense/receive data effective signal input of router side (High active) Carrier sense/receive data effective signal input of WAN side (High active)
REFCLK
Reference Clock
I
TXD0A TXD1A TXD0B TXD1B TXENA TXENB RXERA RXERB RXD0A RXD1A RXD0B RXD1B CRSA CRSB
Transmit Data for Router Side Transmit Data for WAN Side Transmit Enable for Router Side Transmit Enable for WAN Side Receive Error for Router Side Receive Error for WAN Side Receive Data for Router Side Receive Data for WAN Side Carrier Sense / Receive Data Valid for Router Side Carrier Sense / Receive Data Valid for WAN Side
O O O O I I I I I I
Note : The detection of the collision in half duplex is achieved by taking AND of CRS and TXEN.
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MB86978A
* MII interface (2 port) Symbol TXCLKA TXCLKB
Pin name
I/O I I O O O O I I I I I I I I I I I I
Description Clock input for transmission of router side 2.5 MHz at 10BASE, 25 MHz at 100BASE Clock input for transmission of WAN side 2.5 MHz at 10BASE, 25 MHz at 100BASE Transmission data bus of router side The lower two bits are shared with RMII. Transmission data bus of WAN side The lower two bits are shared with RMII. Transmission data effective signal output of router side (High active) Transmission data effective signal output of WAN side (High active) Clock input for reception of router side 2.5 MHz at 10BASE, 25 MHz at 100BASE Clock input for reception of WAN side 2.5 MHz at 10BASE, 25 MHz at 100BASE Reception error input of router side Shared with RMII. (High active) Reception error input of WAN side Shared with RMII. (High active) Receive data effective signal input of router side (High active) Receive data effective signal input of WAN side (High active) Carrier sense signal input of router side (High active) Carrier sense signal input of WAN side (High active) Receive data bus of router side The lower two bits are shared with RMII. Receive data bus of WAN side The lower two bits are shared with RMII. Collision detection input signal for router side (High active) Collision detection input signal for WAN side (High active)
TX CLOCK for Router Side TX CLOCK for WAN Side
TXD0A to TXD3A Transmit Data for Router Side TXD0B to TXD3B Transmit Data for WAN Side TXENA TXENB RXCLKA RXCLKB RXERA RXERB RXDVA RXDVB CRSA CRSB Transmit Enable for Router Side Transmit Enable for WAN Side RX CLOCK for Router Side RX CLOCK for WAN Side Receive Error for Router Side Receive Error for WAN Side Receive Data Valid for Router Side Receive Data Valid for WAN Side Carrier Sense for Router Side Carrier Sense for WAN Side
RXD0A to RXD3A Receive Data for Router Side RXD0B to RXD3B Receive Data for WAN Side COLA COLB Collision Detect for Router Side Collision Detect for WAN Side
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MB86978A
* SMI interface Symbol MDCA
Pin name
I/O O
Description SMI clock output Connect to the SMI clock of the PHY device.
Management Data Clock for PHY Device Management Data input/output for PHY Device Management Data Clock for Direct MII Connection Management Data input/output for Direct MII Connection
MDIOA
SMI data input/output I/O Connect to SMI data of the PHY device. This terminal is connected by wire to multiple PHY devices. I SMI clock input (direct MII) Used when connecting MII directly and not via PHY device. Input the SMI clock output from the opposing SMI controller.
MDCB
MDIOB
SMI data input/ output (direct MII) I/O Used when connecting MII directly and not via PHY device. Connect it with the SMI data signal.
* Others Symbol XRST CLK TRST TMS TCK TDI TDO VPD XTCK VDDE VDDI GND Pin name System Reset System Clock JTAG Reset JTAG Mode JTAG Clock JTAG Data Input JTAG Data Output I/O I I I I I I O I Reset input signal Clock input signal Reset input signal for JTAG (33 k Pull-up in the I/O cell). Input the same reset signal as XRST. Mode setting signal for JTAG (33 k Pull-up in the I/O cell). Clock input signal for JTAG (33 k Pull-up in the I/O cell). Data input signal for JTAG (33 k Pull-up in the I/O cell). Data output for JTAG Connect to ground. 3.3 V system power supply terminal 1.8 V system power supply terminal Grand terminal Description
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MB86978A
BLOCK DIAGRAM
Encryption block
DES/3DES
SMI block
SMI I/F
WAN side MAC block
AES MAC Control RMII/MII
Authentication block
HMAC-SHA-1 HMAC-MD5
Tx/Rx Buffer
Router side MAC block
MAC Control Tx/Rx Buffer RMII/MII
IKE support engine block Extension SADB interface block
ESA I/F
SA data base block
Classifier SADB
Host CPU interface block
Host I/F
Packet buffer
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MB86978A
BLOCK DESCRIPTION
* Encryption block The block with the encoding function and the decoding function of DES, 3DES, and AES used when IPsec is processed.
* Authentication block
The block with the HMAC-SHA-1-96 and HMAC-MD5-96 function used when IPsec is processed.
* IKE support engine block
The block with the following each engine that host CPU uses in the IKE phase. DES/3DES : Encryption engine AES SHA-1 MD5 : Encryption engine : Authentication engine : Authentication engine
IKE support : Surplus operation engine for RSA and DH processing acceleration
* SA data base block
Contains an internal classifier table for selecting the IPsec SA. When a packet is received, the SA corresponding to the selector set in the classifier table is selected. An internal database (SADB table) is also provided to store the policy and parameters to use for IP processing based on the selected SA.
* Packet buffer
This is the buffer to maintain the received packet and the packet before it transmits temporarily.
* Host CPU interface block
This is the interface block for connecting to the host CPU. This block is also used for register read/write and handling of log data. An interrupt signal and status register are used to notify the host CPU when a packet is received.
* Extension SADB interface block
This block controls the local interface used when an extension SADB is connected externally to increase the number of SAs.
* MAC block
Packets are transmitted and received via the RMII or MII interface. The Layer 2 (MAC) functions specified by IEEE 802.3 are executed. One port are on the WAN side and the router side.
* SMI block
This block reads from and writes to the PHY register via the SMI interface. The block is used to setup the PHY device as well as to retrieve status data (half/full duplex, link status, 10/100BASE-T/TX indicator, etc.) from the PHY register. The structure permits direct connection via the MII and CPU on the routing function side.
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MB86978A
SYSTEM CONFIGURATION
* Example of security gateway configuration using the MB86978A
CPU
Routing function
RMII/MII RMII/MII RMII/MII SRAM IF
IPsec function
MB86977 (IP forwarding engine)
RMII/MII
MB86978A (IPsec engine)
RMII/MII
LAN side Interactive full wire (100 Mbps)
WAN side
* Example of configuration using the MB86979 (extended classifier) Max 8
Maximum number of SA supported when used standalone is 64 (Encode SA : 64/Decode SA : 64)
MB86979 (extension SADB) Number of SA : 512
MB86979 (extension SADB) Number of SA : 512
MB86979 (extension SADB) Number of SA : 512
MB86978A
ESA I/F
Extended SADB Chip Bus
Connected to ESAI/FI Number of SA supported when standalone is 512 (Encode SA : 512/Decode SA : 512) Up to 8 can be connected
Number of SA : 64
Note : The SA database inside MB86978A cannot be used if eight MB86979s are used.
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MB86978A
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage*1 Input voltage*
1
Symbol VDDI*2 VDDE* VI VO Tstg Tj IO
3
Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 - 55 - 40 - 10 Max + 2.5 + 4.0 VDDE + 0.5 VDDE + 0.5 + 125 + 125 + 10
Unit V V V V C C mA
Output voltage*1 Storage temperature Operation junction temperature Output current*
4
*1 : This parameter is based on VSS = 0 V. *2 : 1.8 V system power supply *3 : 3.3 V system power supply *4 : DC current that persists for 10 ms or longer or average DC current. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage "H" level input voltage "L" level input voltage Operating temperature Symbol VDDI VDDE VIH VIL Ta Value Min 1.65 3.0 2.0 - 0.3 - 20 Typ 1.8 3.3 Max 1.95 3.6 VDDE + 0.3 + 0.8 + 85 Unit V V V V C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB86978A
DC CHARACTERISTICS
(VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Symbol Conditions Unit Min Typ Max IDD IDDS VOH VOL IL State of operation State of non-operation "H" output current IOH = - 100 A "L" output current IOL = - 100 A VDDE = 3.3 V 0.3 V VDDE = 3.3 V 0.3 V -5 VDDE - 0.2 0 * * +5 450 10 VDDE 0.2 mA mA V V mA
Parameter Power supply current "H" level output voltage "L" level output voltage "H" level output V-I characteristic "L" level output V-I characteristic Input leak current
* : Please refer to the figure below.
"H" level output V-I characteristic
VOH - VDDE [V]
- 4.0 - 3.0 - 2.0 - 1.0 0.0 0 80
"L" level output V-I characteristic
- 20
60
Max Typ
Min
IOH [mA] IOL [mA]
- 40 40
Typ
- 60
Min
20
Max
- 80 0 0.0 1.0 2.0 3.0 4.0
VOL [V]
Note : Conditions : Min : Process = Slow, Tj = + 125 C, VDDE = 3.0 V Typ : Process = Typical, Tj = + 25 C, VDDE = 3.3 V Max : Process = Fast, Tj = - 40 C, VDDE = 3.6 V
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MB86978A
AC CHARACTERISTICS
(1) Host interface data read timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max Chip selection input setup time Chip selection input holding time Read enable input setup time Read enable input hold time Address input setup time Address input holding time Read data output delay time Read data output hold time t1 t2 t3 t4 t5 t6 t7 t8 5 5 5 5 5 5 16 5 ns ns ns ns ns ns ns ns
CLK t1 XCS XWE t3 XRE t5 ADD10 to ADD2 D31 to D0 t7 3 cycles t6 t8 t4 t2
Note : When both XCS and XRE are Low, output enable.
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MB86978A
(2) Host interface data write timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max Chip selection input setup time Chip selection input holding time Write enable input setup time Write enable input holding time Address input setup time Address input holding time Write data input setup time Write data input hold time t1 t2 t3 t4 t5 t6 t7 t8 5 5 5 5 5 5 5 5 ns ns ns ns ns ns ns ns
CLK t1 XCS t3 XWE XRE ADD10 to ADD2 t7 D31 to D0 t8 t4 t2
t5
t6
Note : D31 to D0 are decided by the rising edge of the first "CLK" which the "XWE" signal decided.
(3) Host interface and interruption timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max Interrupt signal output delay time t1 15 ns
CLK t1 XINT t1
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MB86978A
(4) Reset Timings (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max Reset assert time Access barred time after reset deassertion t1 t2 5 20000 clock cycle clock cycle
CLK t1 XRST t2
(5) MII interface data transmission timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max TXENA, TXENB output delay time TXD3A to TXD0A, TXD3B to TXD0B output delay time t1 t2 20 20 ns ns
TXCLKA (TXCLKB) TXENA (TXENB) TXD3A to TXD0A (TXD3B to TXD0B) n-1
t1
n t2
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MB86978A
(6) MII interface data reception timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max RXDVA, RXDVB input setup time RXDVA, RXDVB input holding time RXD3A to RXD0A, RXD3B to RXD0B input setup time RXD3A to RXD0A, RXD3B to RXD0B input holding time RXERA, EXERB input setup time RXERA, EXERB input holding time t1 t2 t3 t4 t5 t6 3 3 3 3 3 3 ns ns ns ns ns ns
RXCLKA (RXCLKB) RXDVA (RXDVB) RXD3A to RXD0A (RXD3B to RXD0B) n-1 t3
t2
t1
n t4
RXCLKA (RXCLKB) RXERA (RXERB)
t6 t5 t6
t5
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MB86978A
(7) SMI interface (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max SMI data input setup time SMI data input hold time SMI data output delay time SMI turning on delay time (Input mode Output mode) SMI turning off delay time (Output mode Input mode) t1 t2 t3 t4 t5 10 10 90 90 90 ns ns ns ns ns
MDCA (MDCB) MDIOA (INPUT) (MDIOB)
t1
t2 t1 t2
MDCA (MDCB) MDIOA (OUTPUT) (MDIOB)
t3
t3
MDCA (MDCB) MDIOA (INPUT OUTPUT) (MDIOB) Input Mode Output Mode t4
MDCA (MDCB) MDIOA (OUTPUT INPUT) (MDIOB) Output Mode t5 Input Mode
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MB86978A
(8) RMII interface (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max RXD1A, RXD0A, RXD1B, RXD0B input setup time RXD1A, RXD0A, RXD1B, RXD0B input holding time CRSA, CRSB input setup time CRSA, CRSB input holding time TXENA, TXENB output delay time TXD1A, TXD0A, TXD1B, TXD0B output delay time t1 t2 t3 t4 t5 t6 4 4 4 4 15 15 ns ns ns ns ns ns
REFCLK CRSA (CRSB) RXD1A, RXD0A (RXD1B, RXD0B) t1 t2
REFCLK t3 CRSA (CRSB) RXD1A, RXD0A (RXD1B, RXD0B) t4
REFCLK t5 TXENA (TXENB) TXD1A, TXD0A (TXD1B, TXD0B) t6
t5
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MB86978A
(9) Extended chip interface and SADB data read timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max Read enable output delay time Read enable output holding time Address output delay time Address output holding time Read data input setup time Read data input hold time t1 t2 t3 t4 t5 t6 0 3.4 12 4.1 12 4.1 ns ns ns ns ns ns
SAADD18 to SAADD0 XSARE XSAWE SAD31 to SAD0
0
1
2
3
4
data0 t3 t1 t4 t6
data1
SAADD18 to SAADD0 XSARE XSAWE SAD31 to SAD0
31
data28 t5 t2
data29
data30
data31
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MB86978A
(10) Extended chip interface and SADB data write timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max Write enable output delay time Write enable output holding time Address output delay time Address output holding time Write data output delay time Write data output holding time t1 t2 t3 t4 t5 t6 12 4.1 12 4.1 12 4.1 ns ns ns ns ns ns
SAADD18 to SAADD0 XSARE XSAWE SAD31 to SAD0 data0 t1
add0
add1
add2
data1 t3 t5
data2 t2 t4 t6
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MB86978A
(11) Extended chip interface and classifier data read timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max Command valid data output delay time Command valid data output holding time Classifier data input setup time Classifier data input holding time t1 t2 t5 t6 0 4.7 12 4.1 ns ns ns ns
XCMDDVE, XCMDDVD CMDE, CMDD XPKTE, XPKTD XMATCHE, XMATCHD CLD0E to CLD3E, CLD0D to CLD3D
Command for table setting (read) Read data
t1
t2
t3
t4
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MB86978A
(12) Extended chip interface and classifier data write timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max Command valid output delay time Command valid output holding time Write command output delay time Write command output holding time Data output delay time Data output holding time t1 t2 t3 t4 t5 t6 12 4.1 12 4.1 12 4.1 ns ns ns ns ns ns
XCMDDVE, XCMDDVD CMDE, CMDD XPKTE, XPKTD XMATCHE, XMATCHD CLD0E to CLD3E, CLD0D to CLD3D t1 t5
Data for table setting Command for table setting (write)
t3 t6
t2 t4
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MB86978A
(13) Extended chip interface and classifier timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 20 C to + 85 C) Value Parameter Symbol Unit Min Typ Max Packet valid output delay time Packet valid output holding time Write command output delay time Write command output holding time Match signal input setup time Match signal input holding time Data output delay time Data output holding time t1 t2 t3 t4 t5 t6 t7 t8 0 2.9 12 4.1 12 4.1 12 4.1 ns ns ns ns ns ns ns ns
XCMDDVE, XCMDDVD CMDE, CMDD XPKTE, XPKTD XMATCHE, XMATCHD CLD0E to CLD3E, CLD0D to CLD3D t1
packet
packet
t5
t4 t8
t3 t7
t2
Note : The match_n signal is asserted low when the packet classifier starts. De-asserted to high when matches are no longer present.
XCMDDVE, XCMDDVD CMDE, CMDD XPKTE, XPKTD XMATCHE, XMATCHD CLD0E to CLD3E, CLD0D to CLD3D
t7
t8
Note : The Valid signal of the result is generated in the main body chip. It doesn't exist outside of the chip.
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MB86978A
NOTES ON HARDWARE SETTING
(1) Power on/off The following sequence is recommended. * Power-ON sequence 1) VDDI (internal) 2) VDDE (external) 3) Signal * Power-OFF sequence 1) Signal 2) VDDE (external) 3) VDDI (internal) Take note of the following points relating to turning the power on and off. * VDDE (external) should not be supplied with signals while VDDI (internal) is off; otherwise a through current may flow, causing potential reliability problems of the LSI. * When VDDE (external) returns from the OFF state to the ON state, the circuit may fail to hold its internal state, for example, due to power supply noise. * Initialize the device when turning the power on. (2) Treatment of unused pin When the only MB86978A is used (when the extended SADB LSI is not used) , the input pin for extended SADB and I/O pin should be treated as follows. XMATCHE XMATCHD UPRIE UPRID XSAINTE XSAINTD CLD0 to CLD3E CLD0 to CLD3D SAD0 to CLD31 : pull-up : pull-up : pull-down : pull-down : pull-up : pull-up : pull-up : pull-up : pull-up
Also, following each output pin which is output from MB86978A to SADB is set to N.C. XRSTOUT XCMDDVE CMDE XPKTE XCMDDVD CMDD XPKTD XSAWE XSARE SAADD0 to SAADD18
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MB86978A
(3) Connection method to execute MII direct connection in rooting function side (reference) MB86978A TXENA TXDA3 to TXDA0 RXDA3 to RXDA0 RXERA RXDVA GND COLA CRSA GND GND MDCB MDIOB Rooting function side MII I/F (opposite side) RX_DV RXD3 to RXD0 TXD3 to TXD0 GND TX_EN RX_ER GND GND CRS COL MDC MDIO
Please input the common clock (25 MHz) as corresponding RXCLK and TXCLK to RXCLKA and TXCLKA.
ORDERING INFORMATION
Part number MB86978ABGL-G MB86978ABGL2-G Package 337-pin plastic FBGA (BGA-337P-M02) 288-pin plastic FBGA (BGA-288P-M13) Remarks
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MB86978A
PACKAGE DIMENSION
337-pin plastic FBGA (BGA-337P-M02)
13.000.10(.512.004) 12.00(.472)REF 0.20(.008) S B B 0.50(.020) TYP
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AE J GECA AC AA W U R N L V T PMK HF DB AD AB Y
A 13.000.10 (.512.004) 12.00(.472) REF
4.00(.157) REF
0.50(.020) TYP
0.20(.008) S A (INDEX AREA) 418-o0.300.10 (418-o.012.004)
4.00(.157) REF
o0.08(.003)
M
INDEX SAB
S
0.10(.004) S
0.250.10 (.010.004) (Stand off)
1.150.20 (.045.008) (Seated height)
C
2004 FUJITSU LIMITED B337002S-c-2-2
Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued)
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MB86978A
(Continued) 288-pin plastic FBGA (BGA-288P-M13)
18.000.10(.709.004) 0.20(.008) S B B 0.75(.030) REF
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABAA Y W V U T R P N M L K J H G F E D C B A
0.75(.030) REF A 18.000.10 (.709.004)
3.75(.148) REF
(INDEX AREA) 0.20(.008) S A 1.250.20 0.350.10 (.014.004) (Stand off) (.049.008) (Seated height) S 3.75(.148) REF 324-o0.450.10 (324-o.018.004)
INDEX
o0.08(.003)
M
SAB
0.15(.006) S
C
2004 FUJITSU LIMITED BGA288013S-c-1-1
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
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MB86978A
FUJITSU LIMITED
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F0511 (c) 2005 FUJITSU LIMITED Printed in Japan

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